Gen-3 Wideband Real-Time Adaptive Full-Duplex Radio

Wide-scale deployment of full-duplex (FD) wireless networks requires analog SI canceller designs suitable for small-form-factor integration within an RF integrated circuit (RFIC). The core technical challenge of analog SI cancellation is accurately reproducing the large delay spreads imposed by the multipath SI channel – a problem that has seen meaningful progress in IC design in recent years. However, RFIC capability alone is only one piece of the puzzle: it is the system-level challenges surrounding a practical FD radio that have thus far prevented widespread FD adoption.

Analog cancellation performance degrades sharply with increasing signal bandwidth, requiring more complex RFIC architectures with a larger number of independent parameters that can accurately model the SI channel’s multipath structure across the wider band. Precisely configuring these parameters in real time is non-trivial: the configuration space grows exponentially, and tuning must account not only for the instantaneous SI channel but also for the specific hardware characteristics of individual devices, which vary due to inherent manufacturing imperfections. The dynamic SI channel further complicates this: motion by the FD node or nearby scatterers will perturb the multipath coupling structure, requiring the canceller to adapt. Computationally efficient algorithms capable of configuring a wideband RFIC canceller in real time, and adaptively maintaining cancellation as the channel evolves without disrupting the data link, are therefore a prerequisite for practical FD deployment.

We address these challenges by presenting the integration of a wideband, time-domain, RFIC-based RF canceller [1, 2] as the frontend of a Software-Defined Radio (SDR)-based FD radio. To enable real-time adaptive RF SIC, we employ a novel globally- and locally-sparse reconstruction-based configuration algorithm, implemented on an FPGA parallel to the FD node’s signal processing workflow. Preliminary versions of this system were demonstrated in [3, 4], and this work won First Place at the ACM SIGCOMM Student Research Competition (SRC).

The RFIC canceller is implemented in a standard 64 nm CMOS process. Tx power is capacitively coupled into the RFIC canceller, which is composed of 16 switched-capacitor-based delay taps. The taps fall into three classes as shown in Table 1: (i) one zero-delay tap with direct input-output connection, (ii) five low-delay taps providing up to 2 ns delay with 250 ps resolution across a 1 GHz bandwidth, and (iii) ten high-delay taps providing up to 8 ns delay with 250 ps resolution across a 1 GHz bandwidth. The tap outputs are weighted, summed, and injected into Rx to achieve cancellation. Intuitively, the RFIC canceller realizes an adaptive FIR filter with sixteen parallel taps of tunable gain and delay.

Rather than relying on the canceller's idealized circuit model — which we show deviates significantly from measured tap behavior — we developed a data-driven configuration algorithm that uses measured, device-specific tap responses directly:

• Initial selection: Globally-Locally Constrained Orthogonal Matching Pursuit (GLC-OMP), a greedy sparse-reconstruction algorithm that selects an initial set of taps, delays, and gains from measured SI channel data, subject to global and per-tap sparsity constraints.
• Iterative refinement: A projected gradient descent (PGD) stage that fine-tunes gains in real time as the SI channel evolves.

The optimization algorithm runs on an FPGA operating in parallel with a GNU Radio-based communications flowgraph, decoupling SI cancellation from the Tx/Rx signal path to avoid added latency. The FD radio is composed of:

• USRP X310 SDR, streaming samples to a host PC over 10 GbE, running a custom GNU Radio-based flowgraph [5] with Zadoff-Chu pilot preambles for synchronization and SI channel estimation
• Gen-3 RFIC canceller (16-tap time-domain design, described on the Gen-3 page)
• Zynq UltraScale+ MPSoC ZCU104 FPGA, running the GLC-OMP/PGD configuration algorithm and canceller configuration logic (~495 µs to reconfigure the canceller)
• Bistatic simultaneous transmit and receive antenna interface for passive isolation
• Linear digital SIC stage (truncated Volterra model) to remove residual SI after analog cancellation, implemented in GNU Radio

References

1. Aravind Nagulu, Sasank Garikapati, Igor Kadota, Mostafa Essawy, Tingjun Chen, Arun Natarajan, Gil Zussman, and Harish Krishnaswamy, “Full-duplex receiver with wideband multi-domain FIR cancellation based on stacked-capacitor, N-path switched-capacitor delay lines achieving >+54dB SIC Across 80MHz BW and >+15dBm TX power handling,” in Proc. IEEE ISSCC’21, Feb. 2021. [download]
2. Sasank Garikapati, Aravind Nagulu, Igor Kadota, Mostafa Essawy, Tingjun Chen, Shibo Wang, Tanvi Pande, Arun S. Natarajan, Gil Zussman, and Harish Krishnaswamy, "Full-Duplex Receiver with Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines," IEEE Journal of Solid-State Circuits 59, 7 (Jul 2024), 2105–2120. [download]
3. Alon S. Levin, Igor Kadota, Sasank Garikapati, Bo Zhang, Aditya Jolly, Manav Kohli, Mingoo Seok, Harish Krishnaswamy, and Gil Zussman, "Demo: Experimentation with Wideband Real-Time Adaptive Full Duplex Radios," in ACM SIGCOMM'23, New York, NY, Sept. 2023. ACM SIGCOMM Student Research Competition (SRC) Winner – First Place [download]
4. Alon S. Levin, Eliot Flores Portillo, Sasank Garikapati, Ahuva Bechhofer, Bo Zhang, Manav Kohli, Igor Kadota,  Harish Krishnaswamy, Mingoo Seok, and Gil Zussman, "Demo: Achieving Self-Interference Cancellation Across Different Environments," in Proc. ACM MobiCom’24, Washington D.C., Nov. 2024. [download]
5. Alon S. Levin, Manav Kohli, Igor Kadota, Tingjun Chen, Sasank Garikapati, Aravind Nagulu, Mahmood Baraani Dastjerdi, Jin Zhou, Ivan Seskar, Harish Krishnaswamy, Gil Zussman, "Enabling Integrated Circuit-Based Full-Duplex Wireless in GNU Radio," in Proc. GNU Radio Conference, Sept. 2024. [download]